FPGA工程师/FPGA Engineer

到岗时间：不限 婚况要求：不限 FPGA工程师/FPGA Engineer 苏州/Suzhou 岗位职责：Responsibilities: 1、负责 xilinx、actel 系列 FPGA 的逻辑开发、仿真与板级调试。 Develop logic for Xilinx and Actel series FPGAs, including simulation and board-level debugging. 2、配合硬件工程师完成硬件联调 Collaborate with hardware engineers to complete hardware integration and debugging. 3、实现 PCIe、DDR、SPI、IIC、UART、AXI 总线等接口的 IP 集成与逻辑设计。 Implement IP integration and logic design for interfaces such as PCIe, DDR, SPI, IIC, UART, and AXI bus. 4、实现数字向量解析与执行、PMU 控制、GT 高速收发器配置与应用等模块开发。 Develop modules for digital vector parsing and execution, PMU control, and GT high-speed transceiver configuration and application. 5、有ATE板卡开发经验 Experience with ATE (Automatic Test Equipment) board/card development. 任职要求：Requirements: 1、本科及以上学历，5 年以上 FPGA 开发经验。 Bachelor's degree or above with at least 10 years of experience in FPGA development. 2、有半导体测试机厂家的任职经历并主导过量产或交付项目。 Previous experience working for a semiconductor tester manufacturer, with a proven track record of leading mass-production or delivery projects. 3、精通 Verilog，熟练使用 Vivado 及仿真工具；熟悉硬件调试，能看懂原理图和 layout。 Proficient in Verilog, skilled in using Vivado and simulation tools; familiar with hardware debugging and capable of reading schematics and PCB layouts. 4、熟悉 Xilinx UltraScale 、Zynq等系列 FPGA。 Familiar with Xilinx UltraScale, Zynq, and other series FPGAs. 5、掌握PCIe、DDR、SPI、IIC、UART、AXI 、GT口控制的实际开发经验 Practical development experience with PCIe, DDR, SPI, IIC, UART, AXI, and GT transceiver control. 6、熟悉时序约束，时序分析，熟悉数字向量处理流程，熟悉 PMU 控制逻辑。 Familiar with timing constraints and timing analysis; knowledgeable about digital vector processing flow and PMU control logic. 7、能够阅读英文芯片手册及技术文档。 Able to read English chip manuals and technical documents. 8、熟悉半导体测试原理。 Familiar with semiconductor testing principles.